1. Field of the Invention
The present invention relates in general to electronic devices, and more particularly to an imbalanced state retention power gating (SRPG) latch circuit that forces a known state upon power-up depending upon the state being stored to save additional static leakage current.
2. Description of the Related Art
State retention power gating (SRPG) is a way to save static leakage current by powering down a majority of a synchronous digital logic block while maintaining power on the flip flops where the state of the digital logic is saved. Various forms of SRPG flip flops have been disclosed and described. The conventional SRPG configurations were implemented according to an assumption, however, that either state (“0” or “1”) of the flip flop must be saved since it is unknown which state is required to be saved at any given time. The present disclosure challenges this assumption. A common flip flop configuration is a master-slave latch configuration in which a master latch feeds a slave latch. Existing configurations keep the slave latch of each flip flop alive (powered up) to maintain state while the rest of the logic, including each master latch, is power gated. The state saving latches remain powered and thus consume a significant amount of static leakage current in the powered down state.
It is desired to save even more static current by power gating at least some of the slave latches. Due to the unknown state of the data, however, more information is required to be used to make the determination of the whether the power can be gated to the slave latch or not.